Arm Processors

The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in terms of numbers produced.[1][2] They were originally conceived as a processor for desktop personal computers by Acorn Computers, a market now dominated by the x86 family used by IBM PC compatible computers. The relative simplicity of ARM processors made them suitable for low power applications. This has made them dominant in the mobile and embedded electronics market as relatively low cost and small microprocessors and microcontrollers.

Contents:

I. Introduction.

II. Programmers Model

a) The structure of the ARM architecture

b) Processor Modes

c) Register set

d) Exception Handling

III. Instruction Set

IV. System Design

V. Development Tools

VI. References

I. Introduction

The ARM processor core originates within a British computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 8 bit processor used in their BBC computer range, which were widely used in UK schools. None of the 16-bit architectures becoming available at that time met their requirements, so they designed their own 32-bit processor.

Other companies became interested in this processor, including Apple who were looking for a processor for their PDA project (which became the Newton). After much discussion this led to Acorn's processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd.

Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies.

One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design - we are an Intellectual Property (or IP) company. Instead silicon is produced by companies who license the ARM processor design.

II. Programmers Model

a) Structure of ARM Architecture

In the ARM world 16-bits is a "halfword" as the architecture is a 32-bit one, whereas "word" means 32-bits.Its implementation includes 2 instruction sets:

1. 32-bit ARM Instruction Set

2. 16-bit Thumb Instruction Set

Java bytecodes are 8-bit instructions designed to be architecture independent. Jazelle transparently executes most bytecodes in hardware and some in highly optimized ARM code. This is due to a tradeoff between hardware complexity (power consumption & silicon area) and speed.

b) Processor Modes

* The arm has 7 basic operating modes:

1. User : unprivileged mode under which most tasks run

2. FIQ : entered when a high priority (fast) interrupt is raised

3. IRQ : entered when a low priority (normal) interrupt is raised

4. Supervisor : entered on reset and when a Software Interrupt

5. instruction is executed

6. Abort : used to handle memory access violations

7. Undef : used to handle undefined instructions

8. System : privileged mode using the same registers as user mode

c) The ARM register set

ARM has 37 registers in total, all of which are 32-bits long.

* 1 dedicated program counter

* 1 dedicated current program status register

* 5 dedicated saved program status registers

* 30 general purpose registers

However these are arranged into several banks, with the accessible

bank being governed by the processor mode. Each mode can access

* a particular set of r0-r12 registers

* a particular r13 (the stack pointer) and r14 (link register)

* r15 (the program counter)

* cpsr (the current program status register)

and privileged modes can also access

* a particular spsr (saved program status register)

Program Status Registers

1. Condition code flags

 N = Negative result from ALU

 Z = Zero result from ALU

 C = ALU operation Carried out

 V = ALU operation oVerflowed

2. Sticky Overflow flag - Q flag

 Architecture 5TE/J only

 Indicates if saturation has occurred

3. J bit

 Architecture 5TEJ only

 J = 1: Processor in Jazelle state

4. Interrupt Disable bits.

 I = 1: Disables the IRQ.

 F = 1: Disables the FIQ.

5. T Bit

 Architecture xT only

 T = 0: Processor in ARM state

 T = 1: Processor in Thumb state

6. Mode bits

 Specify the processor mode

Program Counter(r15)

ARM is designed to efficiently access memory using a single memory access cycle. So word accesses must be on a word address boundary, halfword accesses must be on a halfword address boundary. This includes instruction fetches.

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